The bi-layer lift-off method is used commercially to fabricate many MEMS and semiconductor device structures and is deployed for metallization processes to fabricate neural probe electrodes. The process utilizes LOR/PMGI plus an imaging resist to create a dual layer masking structure. Uniquely, this structure can be application customized because its composition and dimensions can be tailored for a given material-deposition-design feature objective. Considering the necessary advancement of materials and fabrication options to enable neural implantable devices and micro-electrode arrays (MEAs) this study was undertaken to assess use of bi-layer processing with the insulator material SiO2.
A predictive model for structure optimization based on applied deposition film stress for relevant thicknesses to fabricate conductor line insulation and microelectrode arrays is presented. Also, it introduces a new high temperature bi-layer process using a negative imaging resist capable of maintaining stability during higher temperature insulator deposition. This investigation identifies dimensional targets to fabricate successful bi-layers with sputtered insulators for process optimizing useful structures for MEAs, Michigan type probes and related neural interface microstructures. The new processing capability may enable new neural probe interface designs and features to expand the human – artificial intelligence and machine intersection.
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