(TG-10-01) InAlAs/InGaAs Pseudomorphic High Electron Mobility Transistors Grown by Molecular Beam Epitaxy on the InP Substrate
HUANG Jie, GUO Tian-Yi, ZHANG Hai-Ying, XU Jing-Bo, FU Xiao-Jun, YANG Hao, NIU Jie-Bin, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029
School of Physical Science and Technology, Southwest University, Chongqing 400715
CHIN. PHYS. LETT. Vol. 27, No. 11  118502, 2010

(TG-07-01) Fabrication of 22 nm T-gates for HEMT applications
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S. Bentley, X. Li, D.A.J. Moran and I.G. Thayne
Nanoelectronics Research Centre, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, G12 8LT, United Kingdom
Microelectronic Engineering, Volume 85, Issues 5-6, May-June 2008, Pages 1375-1378
Proceedings of the Micro- and Nano-Engineering 2007 Conference – MNE 2007

(TG-07-02) Fabrication of 35-nm Zigzag T-gate Al0.25Ga0.75As/In0.2Ga0.8As/GaAs pHEMTs
Kang-Sung Lee, Young-Su Kim, Yun-Ki Hong, and Yoon-Ha Jeong
Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Hyoja-dong, Nam-gu, Pohang, Gyungbuk, Republic of Korea
IEEE Nanotechnology Materials and Devices Conference, 2007

(TG-05-01) Sub-50 nm T-gate pseudomorphic HEMTs using low temperature development method
Kang-Sung Lee, Kyung-Taek Lee, Young-Su Kim, and Yoon-Ha Jeong
Department of Electrical and Electronic Engineering, Pohang University of Science and Technology (POSTECH); National Center for Nanomaterials and Technology (NCNT) Pohang, Kyungbuk, Republic of Korea
Proceedings of 2005 5th IEEE Conference on Nanotechnology, Nagoya, Japan, July 2005

(TG-04-01) High performance of 0.15μm quasi enhancement-mode (E-mode) In0.4GaAs/In0.4AlAs metamorphic HEMTs on GaAs substrate using new triple-gate technology
Dae-Hyun Kim; Hun-Hee Noh; Suk-Jin Kim; Jae-Hak Lee; Ki-Woong Chung; Kwang-Seok Seo;
Indium Phosphide and Related Materials, 2004. 16th IPRM. 2004 International Conference on
Page(s): 374 – 377 (2004)

(TG-04-02) Suppression of kink phenomenon in ultra-high-speed strained InAs- inserted E-mode HEMTs with a new 0.1 μm Y-shaped Pt-buried gate and their impacts on device performance
Dae-Hyun Kim; Tae-Woo Kim; Hun-Hee Noh; Jae-Hak Lee; Wei Feng; Xiaogang Xie; Quangang Du; Jiang Jian; Jong-In Song; Kwang-Seok Seo;
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International Page(s): 1027 – 1030 (2004)

(TG-04-03) Cost Effective T-Gate Process for PHEMT-based MMIC with Large Gate Periphery
B. Hadad2, I. Toledo2, G. Bunin1, J. Kaplun1, M. Leibovitch1, Y. Shapira2 , Y. Knafo2
1. Gal-El (MMIC), P.O.B. 330, Ashdod 77102, Israel, Tel. +972-8-8572739
2. Department of Physical Electronics, Faculty of Engineering, Tel-Aviv University, Ramat-Aviv 69978, Israel
GaAsManTech (2004)

(TG-04-04) Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors
Xin Cao, et. al
Journal of Microelectronic Engineering – Proceedings of the 29th International Conference on Micro and Nano Engineering, Volume 73-74 Issue 1, June 2004

(TG-03-01) Fabrication of ultrashort T gates using a PMMA/LOR/UVIII resist stack
Chen, Y.;   Macintyre, D. S.;   Cao, X.;   Boyd, E.;   Moran, D.;   McLelland, H.;   Holland, M.;   Stanley, C. R.;   Thayne, I.;   Thoms, S.;
Nanoelectronics Research Centre, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, United Kingdom
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
Volume: 21 Issue:6 3012 – 3016, Nov 2003

(TG-02-01) A novel asymmetric gate recess process for InP HEMTs
Robin, F.; Meier, H.; Homan, O.J.; Bachtold, W.; Indium Phosphide and Related Materials Conference, 2002. IPRM. 14th Digital Object Identifier: 10.1109/ICIPRM.2002.1014332 Page(s): 221 – 224, 2002
(TG-02-02) Sub-100 nm T-gates utilizing a single E-beam lithography exposure process
Ainley, Eric S.; Ageno, Scott; Nordquist, Kevin J.; Resnick, Douglas J.
Proc. SPIE Vol. 4690, p. 1150-1163, Advances in Resist Technology and Processing XIX, 2002

(TG-02-03) Millimetre-wave Performance of InAlAs/InGaAs HEMTs using a UVIII/PMMA Bilayer for 70nm T-Gate fabrication
David L.Edgar, Yifang Chen, Fiona McEwan, Helen McLelland, Euan Boyd, David Moran, Stephen Thoms, Douglas Macintyre, Khaled Elgaid, Xin Cao, Colin Stanley, Iain Thayne
Nanoelectronics Research Centre, Dept of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, Scotland UK. (2002)

(TG-00-01) Fabrication of 30 nm T gates using SiNx as a supporting and definition layer
Y. Chen, D. Edgar, X. Li, D. Macintyre, and S. Thoms
J. Vac. Sci. Technol. B 18, 3521 (2000)

(TG-96-01) Electron-beam/ultraviolet hybrid exposure combined with novel bilayer resist system for a 0.15 mm T-shaped gate fabrication process
H. Takanoa) – High Frequency and Optical Semiconductor Division, Mitsubishi Electric Corporation, Itami 664, Japan
H. Nakano, H. Minami, K. Hosogi, N. Yoshida, and K. Sato – Optoelectronic and Microwave Devices Laboratory, Mitsubishi Electric Corporation, Itami 664, Japan
Y. Hirose and N. Tsubouchi – High Frequency and Optical Semiconductor Division, Mitsubishi Electric Corporation, Itami 664, Japan
J. Vac. Sci. Technol. B 14(6), Nov/Dec 1996

(TG-95-01) Novel high-yield trilayer resist process for 0.1 pm T-gate fabrication
A. S. Wakita, C.-Y. Su, H. Rohdin, H.-Y. Liu, A. J. Seeger, and V. M. Robbins
J. Vac. Sci. Technol. 8 13(6), Nov/Dec 1995